This invention relates generally to semiconductor device processing, and more specifically to polishing apparatus and methods for polishing a semiconductor substrate.
Polishing processes, and more specifically chemical-mechanical polishing processes, have been used in the semiconductor industry to prepare both single crystal substrates and silicon on insulator substrates. In addition, chemical-mechanical polishing processes have also been used to planarize various conductive and insulating layers subsequently deposited on these substrates, during the integrated circuit fabrication process. For example, chemical-mechanical polishing has been used to planarize interlevel dielectric layers that lie in between two different levels of metal interconnect.
Planarizing the interlevel dielectric layer, prior to the formation of the next level of interconnect, is highly desirable because it allows the next level of interconnect to be subsequently patterned and etched without the formation of conductive metal stringers, which can electrically short adjacent metal lines, and without the formation of thinned or notched metal lines, which can adversely effect device reliability. Similarly, chemical-mechanical polishing has been used to planarize conductive materials, such as tungsten, copper, and aluminum, to form planar contact plugs, via plugs, and interconnects. In addition, chemical-mechanical polishing has also been used to form trench isolation. In this process, trenches are formed and then subsequently filled with a deposited dielectric layer, such as silicon dioxide.
The dielectric layer is then polished back to form dielectric filled isolation trenches, which are nearly planar with the adjacent active regions. In addition to being planar, the resulting trench isolation is also desirable because it allows the space separating adjacent active regions to be minimized, and thus allows integrated circuits with high device packing densities to be fabricated.
Unfortunately, the conductive and dielectric layers formed on the semiconductor substrate during the integrated circuit fabrication process often cannot be uniformly and economically polished with current polishing equipment and processes. Specifically, portions of the conductive and dielectric layers which lie near the edge of the semiconductor substrate are often under-polished or over-polished, and therefore semiconductor die located in this area, which is known as the edge exclusion, are often lost. These die represent a substantial revenue loss to integrated circuit manufacturers.
It is known in the prior art to use an independently controlled retaining ring to reduce edge exclusion area. However, prior art approaches use complex mechanical arrangements with custom designed seals and sealing arrangements such as diaphragms, bellows, or air bladders. These configurations are costly, require complex control arrangements, and are difficult to assemble. In addition, these configurations can generate non-uniform pressures on a retaining ring due to geometric constraints and/or mechanical stresses, which result from, for example, attachments or deflections. Moreover, these configurations utilize materials and methods that depart from established practices, which require end users to endure costly and lengthy qualification efforts.
Accordingly, a need exists for a lower cost polishing apparatus and polishing process that can polish semiconductor substrates with a reduced edge exclusion in order to increase die yields. Further, it would be beneficial for such apparatus and processes to use materials and methods that do not require extensive qualification or re-qualification efforts by the end-user.